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document # sram128 rev b revised march 2009 p4c1049/p4c1049l high speed 512k x 8 static cmos ram functional block diagram pin conf igurations high speed (equal access and cycle t imes) 15/20/25 ns (commercial) 20/25/35 ns (industrial) 20/25/35/45/55/70 ns (military) low power single 5v10% power supply easy memory expansion using ce and oe inputs common data i/o three-state outputs fully ttl compatible inputs and outputs advanced cmos t echnology automatic power down packages 32-pin ceramic di p (600 mil) 36-pin soj (400 mil) 36-pin f latp ack 36-pin lcc (452 mil x 920 mil) fe atures the p4c1049 is a 4 megabit high-speed cmos static ram organized as 512kx8. the cmos memory requires no clocks or refreshing, and has equal access and cycle times. inputs are fully ttl-compatible. the ram operates from a single 5v10% tolerance power supply. access times as fast as 15 nanoseconds permit greatly enhanced system operating speeds. cmos is utilized to reduce power consumption to a low level. the p4c1049 is a member of a family of pace ram? products offering fast access times. the p4c1049 device provides asynchronous operation with matching access and cycle times. memory locations are specifed on address pins a 0 to a 18 . reading is accom - plished by device selection ( ce) and output enabling ( oe ) while write enable ( we ) remains high. by presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. the input/output pins stay in the high z state when either ce or oe is high or we is low. description solder-seal flat - pack (fs-4), soj (j9, cj2) lcc (l11) dip pin-out inside datasheet
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 2 document # sram128 rev b dc electrical characteristics (over recommended operating temperature & supply voltage) (2) sym parameter value unit v cc power supply pin with respect to gnd -0.5 to +7 v v term terminal voltage with respect to gnd (up to 7.0v) -0.5 to v cc + 0.5 v t a operating temperature -55 to +125 c t bias temperature under bias -55 to +125 c t stg storage temperature -65 to +150 c p t power dissipation 1.0 w i out dc output current 50 ma maximum r atings (1) recommended ope rating conditions grade (2) ambient t emp gnd v cc commercial 0c to 70c 0v 5.0v 10% industrial -40c to +85c 0v 5.0v 10% military -55c to +125c 0v 5.0v 10% cap acitanc es (4) (v cc = 5.0v, t a = 25c, f = 1.0mhz) sym parameter conditions t yp unit c in input capacitance v in =0v 8 pf c out output capacitance v out =0v 8 pf sym parameter t est conditions p4c1049 p4c1049l unit min max min max v ih input high voltage 2.2 v cc + 0.3 2.2 v cc + 0.3 v v il input low voltage -0.3 (3) 0.8 -0.3 (3) 0.8 v v hc cmos input high voltage v cc - 0.2 v cc + 0.3 v cc - 0.2 v cc + 0.3 v v lc cmos input low voltage -0.3 (3) 0.2 -0.3 (3) 0.2 v v ol output low voltage (ttl load) i ol = +8 ma, v cc = min 0.4 0.4 v v oh output high voltage (ttl load) i oh = -4 ma, v cc = min 2.4 2.4 v i li input leakage current v cc = max, v in = gnd to v cc mil -10 +10 -5 +5 a ind/com -5 +5 n/a n/a i lo output leakage current v cc = max, ce = v ih , v ou t = gnd to v cc mil -10 +10 -5 +5 a ind/com -5 +5 n/a n/a i sb standby power supply current (ttl input levels) ce v ih , v cc = max, f = max, outputs open mil 45 40 ma ind/com 40 n/a i sb1 standby power supply current (cmos input levels) ce v hc , v cc = max, f = 0, outputs open v in v lc or v in v hc mil 15 10 ma ind/com 10 n/a n /a = not applicable
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 3 document # sram128 rev b d ata retention characteristics (p4c1049l military t emperature only) d ata retention w a veform sym parameter t est conditions min t yp* v cc = max v cc = unit 2.0v 2.0v v dr v cc for data retention 3.0 v i ccdr data retention current ce v cc -0.2v, v in v cc -0.2v or v in 0.2v 2 3 ma t cdr chip deselect to data retention time 0 ns t r ? operation recovery time t rc ns * t a = +25c t rc = read cycle time ? this parameter is guaranteed but not tested power dissip ation characteristics vs. speed sym parameter t emperature range -15 -20 -25 -35 -45 -55 -70 unit i cc dynamic operating current* commercial 220 185 180 n/a n/a n/a n/a ma industrial n/a 190 185 175 n/a n/a n/a ma military n/a 200 195 185 175 170 165 ma * v cc = 5.5v. tested with outputs open. f = max. switching inputs are 0v and 3v. ce = v il , oe = v ih .
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 4 document # sram128 rev b sym parameter -15 -20 -25 -35 -45 -55 -70 unit min max min max min max min max min max min max min max t rc read cycle time 15 20 25 35 45 55 70 ns t aa address access time 15 20 25 35 45 55 70 ns t ac chip enable access time 15 20 25 35 45 55 70 ns t oh output hold from ad - dress change 3 3 3 3 3 3 3 ns t lz chip enable to output in low z 3 3 3 3 3 3 3 ns t hz chip disable to output in high z 8 9 11 15 20 25 30 ns t oe output enable low to data valid 7 9 10 15 20 25 30 ns t olz output enable low to low z 0 0 0 0 0 0 0 ns t ohz output enable high to high z 7 9 10 15 20 25 30 ns t pu chip enable to power up time 0 0 0 0 0 0 0 ns t pd chip disable to power down time 15 20 25 35 45 55 70 ns ac electrical characteristicsread cycle (v cc = 5v 10%, all temperature ranges) (2) timing w a veform of read cycle no. 1 ( oe controlled) (5) timing w a veform of read cycle no. 2 (address controlled) (5,6)
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 5 document # sram128 rev b timing w a veform of read cycle no. 3 ( ce controlled) (5, 7) notes: 1. stresses greater than those listed under maximum r atings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specifcation is not implied. exposure to maximum rating conditions for extended periods may affect reliability. 2. extended temperature operation guaranteed with 400 linear feet per minute of air fow. 3. transient inputs with v il and i il not more negative than C2.0v and C100ma, respectively, are permissible for pulse widths up to 20 ns. 4. this parameter is sampled and not 100% tested. 5. we is high for read cycle. 6. ce is low and oe is low for read cycle. 7. address must be valid prior to, or coincident with ce transition low. 8. transition is measured 200 mv from steady state voltage prior to change, with loading as specifed in figure 1. this parameter is sampled and not 100% tested. 9. read cycle time is measured from the last valid address to the frst transitioning address. ac characteristicswrite cycle (v cc = 5v 10%, all temperature ranges) (2) sym parameter -15 -20 -25 -35 -45 -55 -70 unit min max min max min max min max min max min max min max t wc write cycle time 15 20 25 35 45 55 70 ns t cw chip enable time to end of write 12 14 18 22 30 35 40 ns t aw address valid to end of write 12 14 16 20 25 35 40 ns t as address setup time 0 0 0 0 0 0 0 ns t wp write pulse width 12 14 16 22 25 30 35 ns t ah address hold time 0 0 0 0 0 0 0 ns t dw data valid to end of write 9 11 13 15 20 25 30 ns t dh data hold time 0 0 0 0 0 0 0 ns t wz write enable to output in high z 8 10 11 15 18 25 30 ns t ow output active from end of write 3 3 3 5 5 5 5 ns
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 6 document # sram128 rev b timing w a veform of write cycle no. 1 ( we controlled) (10,11) notes: 10. ce and we must be low for write cycle. 11. oe is low for this write cycle to show t wz and t ow . 12. if ce goes high simultaneously with we high, the output remains in a high impedance state 13. write cycle time is measured from the last valid address to the frst transitioning address. t iming wa veform of write cycle no. 2 ( ce controlled) (10) ac test conditions truth table input pulse levels gnd to 3.0v input rise and fall times 3ns input timing reference level 1.5v output timing reference level 1.5v output load see figures 1 and 2 mode ce oe we i/o power standby h x x high z standby d out disabled l h h high z active read l l h d out active write l x l high z active
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 7 document # sram128 rev b figure 1. output load figure 2. thevenin equivalent * including scope and test fxture. note: because of the ultra-high speed of the p4c1049/l, care must be taken when testing this device; an inadequate setup can cause a normal function - ing part to be rejected as faulty. long high-inductance leads that cause supply bounce must be avoided by bringing the v cc and ground planes directly up to the contactor fngers. a 0.01 f high frequency capacitor is also required between v cc and ground. to avoid signal refections, proper termination must be used; for example, a 50? test environment should be terminated into a 50? load with 1.73v (thevenin voltage) at the comparator input, and a 116? resistor must be used in series with d out to match 166? (thevenin resistance). ordering inf ormation
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 8 document # sram128 rev b 32-pin dip (c10) 32-pin ceramic di p pin conf iguration
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 9 document # sram128 rev b solder seal f latp ack sidebrazed dual in-line p ackage pkg # c10 # pins 32 (600 mil) symbol min max a - 0.225 b 0.014 0.026 b2 0.045 0.065 c 0.008 0.018 d - 1.680 e 0.510 0.620 ea 0.600 bsc e 0.100 bsc l 0.125 0.200 q 0.015 0.070 s1 0.005 - s2 0.005 - pkg # fs-4 # pins 36 symbol min max a 0.089 0.125 b 0.015 0.019 c 0.003 0.007 d 0.910 0.930 e 0.505 0.515 e1 - 0.530 e2 0.385 0.395 e3 0.055 0.065 e 0.050 bsc l 0.300 0.350 q 0.015 0.038 s - 0.045 m - 0.002 n 36
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 10 document # sram128 rev b soj small outline ic p ackage ceramic soj small outline ic p ackage pkg # j9 # pins 36 symbol min max a 0.130 0.145 a1 0.082 - b 0.015 0.020 c 0.007 0.013 d 0.920 0.930 e 0.050 bsc e 0.435 0.445 e1 0.395 0.405 e2 0.370 bsc q 0.045 0.055 pkg # cj2 # pins 36 symbol min max a 0.120 0.165 b1 0.030r typ b2 0.020 ref b3 0.025 0.045 d 0.816 0.838 e 0.419 0.431 e2 0.360 0.380 e 0.050 bsc e1 0.430 0.454
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 11 document # sram128 rev b re ctangular leadless chi p carrier pkg # l 11 # pins 36 symbol min max a 0.080 0.100 a1 0.054 0.066 b 0.022 0.028 d 0.910 0.930 d1 0.840 0.860 e 0.445 0.460 e .050 bsc l .100 typ l2 0.115 0.135 p - 0.006 r .009 typ
p4c1049/p4c1049l - high speed 512k x 8 static cmos ram page 12 document # sram128 rev b revisions document number sram 128 document title p4c1049/p4c1049l - high speed 512k x 8 static cmos ram rev issue d ate originator description of change or oct-2005 jdb new data sheet a jan-2008 jdb added cj2 ceramic soj package b mar-2009 jdb added c10 ceramic dip package

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